1. Field of the Invention
The invention relates to a phase-locked loop (PLL) circuit. More particularly, the invention relates to a charge-pump PLL circuit with charge calibration.
2. Description of the Related Art
Many electronic and computer systems and components have critical timing requirements that compel generation of periodic clock waveforms that are precisely synchronized with a reference clock waveform. A phase-locked loop (PLL) is one type of circuit that is widely used to provide an output signal having a precisely controlled frequency that is synchronized with the frequency of a received or input signal. Frequency synthesizers, multipliers and dividers, single and multiple clock generators, clock recovery circuits, and wireless communication devices are (but a few) examples of the manifold implementations of PLLs.
FIG. 1 illustrates a block diagram of a typical charge-pump phase-locked loop (CP-PLL) circuit 100. The CP-PLL circuit 100 includes a phase detector 110, a charge-pump circuit 120, a loop filter 130, a voltage-controlled oscillator (VCO) 140 and a frequency divider 150. The CP-PLL circuit 100 receives a reference clock signal CLKref having a frequency Fref and generates an output clock signal CLKout having a frequency Fout that is synchronized with the reference clock signal CLKref in phase. The reference clock signal CLKref is coupled into the phase detector 110, where it is compared with a feedback signal CLKxe2x80x2out. Based on this comparison, the phase detector 110 generates a pump-up signal UP and a pump-down signal DN which, in turn, direct the charge-pump circuit 120 to either source or sink current to or from the loop filter 130 which develops a voltage Vc for adjusting the output frequency of the VCO 140. The output of the VCO 140, which is the output of the CP-PLL circuit 100, is coupled to the frequency divider 150. The feedback signal CLKxe2x80x2out may be the same as the output clock signal CLKout from the VCO 140, or as illustrated in FIG. 1 the feedback signal CLKxe2x80x2out may be the output of the frequency divider 150. Although the frequency divider 150 is commonly used in the CP-PLL circuit 100 to divide the frequency received from the VCO 140 by N, it may be eliminated in certain applications.
The charge pump 120 generates a current ICP that develops the voltage Vc across the loop filter 130. The current ICP is dependent on the UP and DN signals from the phase detector 110. When the rising edge of CLKref leads the rising edge of CLKxe2x80x2out, the charge-pump circuit 120 increases ICP to develop a larger Vc across the loop filter 130 which, in turn, causes the VCO 140 to increase the frequency of CLKout. Conversely, when CLKref lags CLKxe2x80x2out, the charge pump 120 decreases ICP to develop a smaller Vc across the loop filter 130 which, in turn, causes the VCO 140 to decrease the frequency of CLKout. When the feedback frequency Fxe2x80x2out is ultimately locked onto the reference frequency Fref, i.e. the phases of the two signals CLKref, CLKxe2x80x2out are aligned, the voltage Vc is not adjusted and the output frequency Fout is kept constant. In this state, the CP-PLL circuit 100 is said to be in a xe2x80x9clockedxe2x80x9d condition.
The charge-pump circuit 120 internally delivers a pump-up current and a pump-down current in response to the UP and DN signals. Therefore, the charge pump output current ICP is the sum of the pump-up and pump-down currents. Ideally, if the CP-PLL circuit 100 is xe2x80x9clockedxe2x80x9d and no change in the output frequency Fout is needed, the pump-up current and the pump-down current cancel each other and no net current ICP is produced. Nevertheless, manufacturing process variations, ambient conditions and inherent device characteristics can cause the pump-up current and the pump-down current to mismatch. This current mismatch results in a residual charge being left on the loop filter 130 and further causes the voltage Vc applied to the VCO 140 to fluctuate. As a result, the PLL output signal CLKout produces clock jitter. In addition to current mismatch, charge injection and loop filter leakage are sources of charge accumulation on the loop filter 130 which prevent the CP-PLL circuit 100 from being precisely locked.
In view of the above, there is a need for a charge-pump PLL that overcomes the problems of the prior art.
It is an object of the present invention to provide a CP-PLL circuit with charge calibration to eliminate a residual charge so that the CP-PLL circuit keeps its output frequency constant.
According to one aspect of the invention, a CP-PLL circuit with charge calibration includes a charge-pump circuit and a calibration circuit. The charge-pump circuit provides a charge-pump output current to cause an output clock signal""s phase to track a reference clock signal""s phase. The calibration circuit is made up of a sensing means for sensing a net charge delivered from the charge-pump output current and an adjusting means for generating a calibrate voltage signal. The calibrate voltage signal has a value in proportion to an amount of the net charge sensed by the sensing means. The charge-pump circuit also includes a regulating means for fine tuning the charge-pump output current based on the calibrate voltage signal to eliminate the net charge. Under control of the calibrate voltage signal, the charge-pump circuit cooperating with the regulating means regulates the net charge to become exactly zero, thereby maintaining the phase of the output clock signal locked onto the phase of the reference clock signal.
In one embodiment of the present invention, a CP-PLL circuit with charge calibration is carried out. The CP-PLL circuit includes a first charge-pump circuit and a calibration circuit. The first charge-pump circuit provides a first current to cause an output clock signal""s phase to track a reference clock signal""s phase. The first charge-pump circuit is comprised of a first source current mirror, a first sink current mirror and a first transistor. The first source current mirror provides a first pump-up current and the first sink current mirror provides a first pump-down current, in which the first current is the sum of the first pump-up and the first pump-down currents. The first transistor is arranged in cascade connection with the first charge-pump circuit to fine tune the first current based on a calibrate voltage signal in order to eliminate a first net charge delivered from the first current.
The calibration circuit includes a second charge-pump circuit and a charge sensing circuit. The second charge-pump circuit is configured to provide a second current to simulate the first current in a condition in which the phase of the output clock signal is locked onto the phase of the reference clock signal. A second transistor is preferably arranged in cascade connection with the second charge-pump circuit. It fine tunes the second current based on the calibrate voltage signal to eliminate a second net charge delivered from the second current. According to the first and the second net charges, the charge sensing circuit generates the calibrate voltage signal and provides it as feedback to the first and the second charge-pump circuits. Under control of the calibrate voltage signal, the first and the second charge-pump circuits respectively regulate the first and the second net charges to become exactly zero, thereby maintaining the phase of the output clock signal locked onto the phase of the reference clock signal.